1. Field of the Invention
The present invention relates to a plasma display panel, and more specifically, a method and an apparatus for driving a plasma display panel.
2. Description of the Background Art
A plasma display panel (hereinafter, referred to as “PDP”) displays images including characters or graphics since fluorescent material is emitted by ultraviolet rays of 147 nm occurring when inert mixed gases of He+Xe, Ne+Xe, He+Ne+Xe, etc. are discharged. It is easy for this PDP to be made thin and large. The PDP also provides an improved picture quality due to recent advanced technology. In particular, in a 3-electrode AC sheet discharge PDP, wall charges are accumulated on the surface of the PDP upon the discharge of the PDP and electrodes are protected from sputtering occurring due to the discharge. Therefore, the 3-electrode AC sheet discharge PDP advantageously has a low-voltage driving and a long life span.
FIG. 1 shows a schematic diagram illustrating an arrangement of electrodes in a plasma display panel. FIG. 2 shows a perspective view illustrating a discharge cell structure of a 3-electrode ac surface discharge plasma display panel.
As shown in FIG. 1 and FIG. 2, a 3-electrode ac surface discharge PDP includes scan electrodes Y1 through Yn and sustain electrodes Z which are formed on an upper substrate, and address electrodes X1 through Xm which are formed on a lower substrate.
Discharge cells 1 of the PDP are formed at the crossing areas of the scan electrodes Y1 through Yn, the sustain electrodes Z, and the address electrodes X1 through Xm.
Each of the scan electrodes Y1 through Yn and the sustain electrodes Z includes transparent electrodes 12, and metal bus electrodes 11 of which width is less than those of the transparent electrodes 12 and which are formed in an edge region of one side of the transparent electrodes. The transparent electrodes 12 are usually made of indium-tin-oxide (hereinafter, referred to as “ITO”) and formed on the upper substrate 10.
The metal bus electrode 11, usually metal, are formed on the transparent electrodes 12 and serve to reduce a voltage drop by the transparent electrodes 12 having a high resistance. An upper dielectric layer 13 and a protection film 14 are stacked on the upper substrate 10 on which the scan electrodes Y1 through Yn and the sustain electrodes Z are formed. Wall charges which are generated in plasma discharge are stacked on the upper dielectric layer 13. The protection film 14 serves to prevent damage of the electrodes Y1 through Yn, Z and the upper dielectric layer 13 due to sputtering occurred upon the plasma discharge and to increase emission efficiency of secondary electrons. The protection film 14 is usually made of magnesium oxide (MgO).
The address electrodes X1 through Xm are formed in the direction intersecting the scan electrodes Y1 through Yn and the sustain electrodes Z on the lower substrate 18. Lower dielectric layer 17 and a diaphragm 15 are formed on the lower substrate 18. Fluorescent material layer 16 is formed on the surface of the lower dielectric layer 17 and the diaphragm 15. The diaphragm 15 is formed in parallel to the address electrode X1 through Xm, divides the discharge cells physically, and serves to prevent electric or optical interferences between the neighboring discharge cells 1. The fluorescent material layer 16 is excited by ultraviolet rays, which are generated upon the plasma discharge, and generates a visible ray of one of red, green and blue.
Inert mixed gas such as He+Xe, Ne+Xe or He+Ne+Xe for discharge is inserted into a discharge space of the discharge cell formed between the upper/lower substrates 10, 18 and the diaphragm 15.
In such a 3-electrode AC sheet discharge type PDP, one frame is driven with it divided into several sub-fields having different numbers of emission in order to implement the gray level of a picture. As shown in FIG. 3, if it is desired to display a picture using 256 gray scales, the frame period 16.67 ms corresponding to 1/60 second is divided into eight sub-fields SF1 to SF8. Each sub-field SF1 through SF8 is divided into a reset period during which the discharge cells are initialized, an address period during which the discharge cells are selected, and a sustain period which gray level is implemented by the number of discharge. The reset and address period of each sub-field are same in every sub-field, whereas the sustain period and the number of the discharge are increased in the ratio of 2n (n=0, 1, 2, 3, 4, 5, 6, 7) in each sub-field.
FIG. 4 shows a waveformform illustrating the driving method of a plasma display panel. As shown in FIG. 4, during setup period SU of the reset period, rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y. At the same time, 0[V] is applied to the sustain electrodes Z and the address electrodes X. Setup discharge, little discharge, is generated between the scan electrodes and the address electrodes, or between the scan electrodes and the sustain electrodes in the cells of total screen by the rising ramp waveform Ramp-up. By this setup discharge, wall charges of positive polarity are stacked on the address electrodes X and the sustain electrodes Z, and wall charges of negative polarity are stacked on the scan electrodes Y. During setdown period SD of the reset period, falling ramp waveform Ramp-dn, which falls from about the sustain voltage Vs to the ground voltage GND or 0[V], is simultaneously applied to the scan electrodes.
While this falling ramp waveform Ramp-dn is applied to the scan electrodes Y, the sustain voltage Vs is applied to the sustain electrodes Z and 0[V], is applied to the address electrodes X. When this falling ramp waveform Ramp-dn is applied, setdown discharge, little discharge, is generated between the scan electrodes Y and the sustain electrodes Z, and between the scan electrodes and the address electrodes. By this setdown discharge, wall charges, which are unnecessary for address discharge among wall charges formed by setup discharge, are erased.
Examining change of wall charges during the reset period, the change of wall charges on the address electrodes almostly can not be found, and wall charges of negative polarity, which are formed on the scan electrodes by the setup discharge, are erased partly. On the other side, on the sustain electrodes Z, wall charges of positive polarity was formed by the setup discharge. However, wall charges of negative polarity are stacked as many as the reduction quantity of negative polarity wall charges of the scan electrodes by the setdown discharge.
During the address period, the scan pulse SP of the negative polarity is sequentially applied to the scan electrodes Y and at the same time the data pulse DP of the positive polarity is synchronized with the scan pulse SP and applied to the address electrodes X. As the voltage difference between the scan pulse SP and the data pulse DP and the wall voltage generated in the reset period are added, an address discharge is generated within a cell to which the data pulse DP is applied. Wall charges are generated within the cell selected by the address discharge and the wall charges can generate discharge by applying the sustain voltage Vs. During this address period, positive polarity dc voltage Zdc is applied to the sustain electrodes Z.
During the sustain period, sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. Then, in the cell selected by the address discharge, sustain discharge, that is display discharge, is generated between the scan electrodes Y and the sustain electrodes Z every time when every sustain pulse is applied, while the wall voltage and the sustain pulse SUS within the cell are added thereto.
In the erase period following the sustain period, wall charges, which remain in the cells of the total screen, are erased by applying the erase ramp waveform RAMP-ERS, of which the pulse width is narrow and the voltage level is low, to the sustain electrodes Z.
In case that the voltage of the falling ramp waveform falls only to zero 0[V] like the driving waveform of FIG. 4, the erasing work, by which the wall charges, which is necessary for the address discharge, are leaved uniformly in the all discharge cells, is not achieved well. Because of this, the method, through which the voltage of the falling ramp waveform falls to negative polarity voltage and the erasing discharge is achieved enoughly and uniformly, has been developed.
Recently, the pixel of the PDP is rising and the picture quality of the PDP is being improved. However, as the subfield is added for rising the pixel or improving the picture quality, the address driving time becomes longer and the driving time for the PDP becomes insufficient. This insufficiency of driving time for the PDP can be solved by dual-scan method which can scan two lines simultaneously. However, in this dual-scan method, Drive Integrated Circuit must be added. Therefore, recently, the research for improving the picture quality by using single scan is being advanced actively.
Further, recently, for improving efficiency of PDP, a method, which increases the content of Xe more than 10%, was proposed. However, if the content of Xe is increased like this, the ramp voltage of the reset period increases and the discharge is delayed. Specially, as the value of the address jitter is increased, the scan period and the address period is increased, PDP can not be drived by single scan, the driving margin becomes smaller, and the sustain work becomes unstable.